1. Field of the Invention
The present invention generally relates to a semiconductor memory device and a method of testing a semiconductor memory device. More specifically, the present invention relates to a semiconductor memory device with a reduced number of input/output terminals to be used for operation test and a method of testing the semiconductor memory device.
Priority is claimed on Japanese Patent Application No. 2008-0143580, filed May 30, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
In general, test for semiconductor memory devices such as DDR-SDRAM has been performed as follows. Data as supplied from the outside are written or stored into a predetermined memory area of the semiconductor memory device. The stored data are then read out of the memory area and then supplied to the outside.
FIG. 14 is a schematic diagram illustrating a semiconductor memory device 91 and a tester 90 which is connected to the semiconductor memory device 91 in accordance with the related art.
The semiconductor memory device 91 includes a control circuit 911, a memory 912 including a memory cell array, a serial-parallel converter circuit 913, a clock input terminal 915, a control signal input terminal 916, and a plurality of data input/output terminals 917. The plurality of data input/output terminals 917 may be, typically, but not limited to, thirty two data input/output pins.
The tester 90 generates a clock signal, an address signal and a control signal and supplies these signals to the semiconductor memory device 91. Typical examples of the control signal may include any command signals for read and write operations. The tester 90 performs data input and output to the semiconductor memory device 91 through the data input/output terminals 917.
The semiconductor memory device 91 will be described in detail. The control circuit 911 receives an input of the clock signal from the clock input terminal 915 and an input of the control signal from the control signal input terminal 916. The control circuit 911 controls read and write operations to the memory 912 based on the clock signal and the control signal. The memory 912 includes a memory cell array. The serial-parallel converter circuit 913 converts data of 64-bits into a series of data of 32-bits. The data of 64-bits are input into the serial-parallel converter circuit 913 from the memory 912 at the rising edge of the clock signal. The data of 64-bits are also output from the serial-parallel converter circuit 913 at the rising edge of the clock signal and then supplied to the memory 912. The series of data of 32-bits is input into and output from the serial-parallel converter circuit 913 at the rising and falling edges of the clock signal.
FIG. 15 is a schematic diagram illustrating test operation for the semiconductor memory device 91 using the tester 90 in accordance with the related art. In a first time period T901, the tester 90 supplies the control signal including write command and the clock signal to the semiconductor memory device 91, so as to write data of 32-bits into the semiconductor memory device 91. In a second time period T902, the tester 90 supplies the other control signal including read command and the clock signal to the semiconductor memory device 91, so as to receive the input of data of 32-bits from the semiconductor memory device 91. The tester 90 determines whether the input data of 32-bits are identical to a predetermined set of data, so that the tester 90 detects any failure of the semiconductor memory device 91.
In case that the test for the semiconductor memory device is performed in the same way as described above, the increase in the number of the data input/out terminals of the semiconductor memory device needs the increase in the input/out terminals of the tester which are connected to the data input/out terminals of the semiconductor memory device, thereby decreasing the number of the semiconductor memory devices that are together connected to the single tester. Decreasing the number of the semiconductor memory devices that are together connected to the single tester may increase the time to be lapsed for completing the test operation as well as increase the cost for performing the test operation. For example, sixty four semiconductor memory devices with the data input/output terminals for data of 4-bits can be connected together to the tester that has 256 input/output terminals. Bight semiconductor memory devices with the data input/output terminals for data of 32-bits can be connected together to the tester that has 256 input/output terminals.
In other cases, an advanced tester with high resolution to measure a signal with high speed transition may be useful to perform the test operations for semiconductor devices having high speed performances. The semiconductor devices with high speed performances may perform input and output operations at high speed or at high frequencies of 533 MHz and 666 MHz. A typical example of each the semiconductor device may be, but is not limited to, a controller for DDR-SDRAM.
Japanese Unexamined Patent Application, First Publication, No. 2007-317016 discloses a technique for performing the test operation for the semiconductor devices without using the advanced tester, wherein a loop-back circuit is used for feeding back the output from the semiconductor device to the same. FIG. 16 is a schematic diagram illustrating a semiconductor circuit 92 and a tester 90 which is connected to the semiconductor circuit 92 in accordance with the related art. A serial-parallel converter circuit 923 receives an input of data from a control circuit 921. The serial-parallel converter circuit 923 supplies the data to a comparator 924. The comparator 924 receives an input of data from the serial-parallel converter circuit 923. The comparator 924 also receives an input of data from the control circuit 921. The comparator 924 compares two sets of data from the serial-parallel converter circuit 92 and from the control circuit 921. The comparator 924 compares the set of data that is output from the control circuit 921 to the set of data that is output from the serial-parallel converter circuit 923, thereby performing the test operations for the semiconductor circuit 92, without performing operations of high speed input/output of data between the semiconductor circuit 92 and the tester 90.
FIG. 17 is a schematic diagram illustrating a semiconductor circuit 93 and a tester 90 which is connected to the semiconductor circuit 93 in accordance with the related art. The semiconductor circuit 93 includes a control circuit 931, a memory 932 including a memory cell array, a serial-parallel converter circuit 933, a comparator 934, a clock input terminal 935, a control signal input terminal 936, and a plurality of data input/output terminals 937. The semiconductor circuit 93 uses the loop-back circuit for feeding back the output from the semiconductor device to the same. The tester 90 generates a clock signal, an address signal and a control signal and supplies these signals to the semiconductor memory device 93. Typical examples of the control signal may include any command signals for read and write operations. The tester 90 does not perform data input and output to the semiconductor memory device 93.
In the semiconductor circuit 93, the control circuit 931 receives the clock signal from the clock input terminal 935. The control circuit 931 also receives the control signal from the control signal input terminal 936. The control circuit 931 controls the operations of reading and writing data to the memory 932 as well as switches the serial-parallel converter circuit 933, based on the clock signal and the control signal. In the test operations, the control circuit 931 controls the comparator 934 so that the comparator 934 compares the output from the memory 932 with the output from the serial-parallel converter circuit 933, and generates a result of that comparison.
In reading operation, the serial-parallel converter circuit 933 converts data of 64-bits into a series of data of 32-bits and then supplies the series of data of 32-bits to the plurality of data input/output terminals 937. The data of 64-bits are input into the serial-parallel converter circuit 933 from the memory 932 at the rising edge of the clock signal. The data of 64-bits are also output from the serial-parallel converter circuit 933 at the rising edge of the clock signal and then supplied to the memory 932. The series of data of 32-bits are input into and output from the serial-parallel converter circuit 933 at the rising and falling edges of the clock signal.
In writing operation, the serial-parallel converter circuit 933 converts a series of data of 32-bits into data of 64-bits and then supplies the data of 64-bits to the memory 932 and the comparator 934. The series of data of 32-bits are input into the serial-parallel converter circuit 933 from the plurality of data input/output terminals 937 at the rising and falling edges of the clock signal. The data of 64-bits are output from the serial-parallel converter circuit 933 at the rising edge of the clock signal.
In test-result termination, the serial-parallel converter circuit 933 supplies data signals of 64-bits to the comparator 934, wherein the data signals of 64-bits have been input to the serial-parallel converter circuit 933 from the memory 932.
The comparator 934 compares the data signal of 64-bits from the memory 932 to the data signal of 64-bits from the serial-parallel converter circuit 933, so that the comparator 934 generates a result of that comparison.
The tester 90 supplies the clock signal and the control signal including read command to the semiconductor memory device 93. In the semiconductor memory device 93, the control circuit 931 supplies data stored in the memory 932 to the serial-parallel converter circuit 933, based on the clock signal and the control signal including read command. The control circuit 931 controls the serial-parallel converter circuit 933 to supply the data signals to the comparator 934.
The comparator 934 compares the data signals of 64-bits from the memory 932 to the data signals of 64-bits from the serial-parallel converter circuit 933, so that the comparator 934 generates a result of that comparison. The control circuit 931 supplies the result of the comparison from the comparator 934 to the tester 90.
As described above, the serial-parallel converter circuit 933 through which input and output data of the memory 932 axe transferred is subjected to an operation test such as a real operation speed test without performing any high speed input/output operation for data, for example, at 533 MHz or 666 MHz between the semiconductor memory device 93 and the tester 90.